Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components such as dies that are packaged in chip packages. The dies may include memory, logic or other IC devices.
In many chip packages, one or more dies are generally coupled to an interposer that includes a silicon substrate. Such silicon substrate is generally a semiconductor (as opposed to a dielectric), as is also generally known. The interposer is coupled through solder balls to a package substrate for mounting onto a board. To electrically connect the one or more dies to the board, through-silicon vias (TSV's) are formed through the silicon substrate. The TSVs generally comprise holes formed through the silicon substrate that are filled with a conductive material.
In general, TSV's contribute to a relatively large portion of the fabrication cost, time, and complexity of a particular integrated chip package. Manufacturing complexity associated with TSV's results from the fact that forming TSV's require several manufacturing steps that cannot be done simply. TSV's also introduce other issues such as issues related to capacitive loading, issues related to handling during manufacturing, issues related to inspection, and other issues that have to be addressed and that increase design complexity, thus increasing the time and cost for creating a design.
Therefore, a need exists for improved chip packaging.